#!/usr/bin/env python
# Francesco Conti <f.conti@unibo.it>
#
# Copyright (C) 2016-2019 ETH Zurich, University of Bologna.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
# 
#     http://www.apache.org/licenses/LICENSE-2.0
# 
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

from ipstools_cfg import *

execute("mkdir -p sim/vcompile/ips")
execute("rm -rf sim/vcompile/ips/*")
execute("mkdir -p sim/vcompile/rtl")
execute("rm -rf sim/vcompile/rtl/*")
execute("mkdir -p sim/vcompile/tb")
execute("rm -rf sim/vcompile/tb/*")

# creates an IPApproX database
ipdb = ipstools.IPDatabase(rtl_dir='rtl', ips_dir='ips', vsim_dir='sim', load_cache=True)
# generate ModelSim/QuestaSim compilation scripts
ipdb.export_make(script_path="sim/vcompile/ips", more_opts="+define+HWPE_ASSERT_SEVERITY=\"\\$$fatal\"")
ipdb.export_make(script_path="sim/vcompile/rtl", source='rtl')
# generate vsim.tcl with ModelSim/QuestaSim "linking" script
ipdb.generate_vsim_tcl("sim/tcl_files/config/vsim_ips.tcl")
ipdb.generate_vsim_tcl("sim/tcl_files/config/vsim_rtl.tcl", source='rtl')
# generate script to compile all IPs for ModelSim/QuestaSim
ipdb.generate_makefile("sim/vcompile/ips.mk")
ipdb.generate_makefile("sim/vcompile/rtl.mk", source='rtl')
# generate FPGA-related scripts
ipdb.export_verilator("veri/verilate_ips.mk")
ipdb.export_verilator("veri/verilate_rtl.mk", source='rtl')

print(tcolors.OK + "Generated new scripts for IPs!" + tcolors.ENDC)

